G.729 speech codec was standardized by ITU-T in 1996. The codec operates on each 10ms frame of 16-bit speech signals sampled at 8 KHz and generates a compressed bit-stream of 8 kbps. It has a look-ahead delay of 5 ms and uses conjugate-structure algebraic code excited linear prediction (CS-ACELP) algorithm for compression. Annex A of the standard specifies a low complexity version and Annex B specifies a voice activity detection (VAD) algorithm as well the discontinuous transmission mode of operation. In 2005, ITU-T extended the Annex-B to provide additional options for the VAD algorithm. Annex D specifies operation at 6.4 kbps. Annex E specifies operation at 11.8 kbps suitable for music signals. Annex G specifies operation at 8 kbps or 11.8 kbps. The decoder supports an inherent packet loss concealment algorithm. The codec is widely used in VoIP applications.

  • Based on ITU-T specification.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz.
  • Support for 6.4/8/11.8 kbps bit-rate.
  • Support for RTP payload format as specified in RFC 3551.
  • Supports integrated DTX mode of operation configurable at init-time.
  • Support for all the three VAD algorithms, configurable at init-time.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for bad frame indication at frame boundary.
  • The implementation supports both Little-Endian and Big-Endian (on ARM and C64x+ platforms).
  • Optional support for xDM APIs on TI platforms.
  • Tested for bit-exactness with standard as well as a large database of non-standard test vectors.
  • Module is fully interruptible (maximum interrupt latency on C64x+ is 6000 cycles).
  • Tested for any illegal memory access by the module (C64x+ and ARM).
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested with scratch contamination at frame boundaries.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C64x implementation validated on Spectrum Digital C6416 DSK.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • Cortex-M4 implementation validated on the TI Tiva TM4C1294 EVM.
  • AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.

ARM9E, ARM11, Cortex-M4, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, TI C66x, and AMD/Intel 64-bit cores supporting SSE4 and above.

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