G.729.1 speech/audio codec was standardized by ITU-T in 2006. The codec operates on each 20ms frame of 16-bit speech/audio signals sampled at 8 KHz or 16 KHz and generates a compressed bit-stream having bit-rates in the range of 8 kbps  32 kbps structured as 12 layers. The layered approach allows the decoder or any other component in the communication system to truncate the bit-stream by removing the higher layers. The base layer, at 8 kbps, is inter-operable with the G.729 codec. The second layer, at 12 kbps, is the narrowband enhancement layer. Bandwidth extension is added in layer three and predictive transform coding based on MDCT improves the quality from layer four to twelve. The encoder has an inherent support for FEC for bit-rates greater than 12 kbps. The decoder supports the G.729B VAD/DTX scheme has an inherent packet loss concealment algorithm. The codec is primarily targeted for wideband VoIP applications.

  • Based on ITU-T specification
  • Optimized ASM/C implementation (C55x and C64x+, sub-optimal on ARM)
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz or 16 KHz.
  • Support for 8 – 32 kbps bit-rates.
  • Support for encoding G.729 compatible bit-streams.
  • Support for RTP payload format as specified in RFC 4749 and RFC 5459.
  • Supports G.729B VAD/DTX mode of operation configurable at init-time.
  • Support for optional low delay decoding mode, configurable at init-time.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for bad frame indication at frame boundary.
  • The implementation supports both Little-Endian and Big-Endian (on ARM and C64x+ platforms)
  • Optional support for xDM APIs for TI implementations.
  • Tested for bit-exactness with standard as well as a large database of non-standard test vectors.
  • Module is fully interruptible (Maximum interrupt latency on C64x+ is 6000 cycles).
  • Tested for any illegal memory access by the module (C64x+ and ARM).
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Tested for Interoperability.
  • Range validation for all the API parameters.
  • Tested with scratch contamination at frame boundaries.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, TI C64x+,  and TI C66x.

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