G.723.1A speech codec was standardized by ITU-T in 1996. The codec operates on each 30ms frame of 16-bit speech signals sampled at 8 KHz and generates a compressed bit-stream having bit-rates of 5.3 and 6.3 kbps respectively. It has a look-ahead delay of 7.5 ms and uses algebraic code excited linear prediction (ACELP) algorithm for the low bit-rate and Multi-Pulse Maximum Likelihood Quantization (MP-MLQ) algorithm for the high bit-rate modes. Annex A of the standard specifies a voice activity detection algorithm as well the discontinuous transmission mode of operation. The decoder supports an inherent packet loss concealment algorithm. Support for this codec is mandatory for ITU-T H.324 terminals offering audio communication. It is also widely used in VoIP applications.

  • Based on ITU-T specification.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz.
  • Support for 5.3 and 6.3 kbps bit-rates.
  • Support for swapping the bit-rates at frame boundary.
  • Support for optional high-pass filter configurable at init-time.
  • Support for RTP payload format as specified in RFC 3551.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for bad frame indication (CRC) at frame boundary.
  • Support for post-filter operation, configurable at frame boundary.
  • Supports integrated DTX mode of operation configurable at init-time.
  • The implementation supports both Little-Endian and Big-Endian (on ARM and C64x platforms).
  • Optional support for xDM APIs on TI platforms.
  • Tested for bit-exactness with standard as well as a large database of non-standard test vectors.
  • Module is fully interruptible (Maximum interrupt latency on C64x is 6000 cycles).
  • Tested for any illegal memory access by the module (C64x and ARM).
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested with scratch contamination at frame boundaries.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C64x implementation validated on Spectrum Digital C6416 DSK.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • Cortex-M4 implementation validated on the TI Tiva TM4C1294 EVM.
  • AMD/Intel optimized implementation validated on Intel cores supporting SSE4 and above.

ARM9E, ARM11, Cortex-M4, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, TI C66x, and AMD/Intel 64-bit cores supporting SSE4 and above.

For resource requirements & other details