G.718 speech codec was standardized by ITU-T in 2008. The codec operates on each 20 ms frame of 16-bit speech signals sampled at 8 KHz or 16 KHz and generates a compressed bit-stream having bit-rates in the range of 8 – 32 kbps. The encoder has an embedded scalable structure producing a bit-stream structured in five layers corresponding to the bit-rates 8, 12, 16, 24, and 32 kbps respectively. The lower two layers use CELP algorithm to encode while the higher layers are based on overlap-add MDCT transform coding. The encoder supports an integrated DTX/CNG mode operation. When the bit-rate is limited to 12 kbps, the encoder provides an option for noise suppression, and a low-delay mode of operation. The codec also provides an alternative coding mode 12.65 kbps, inter-operable with AMR-WB (G.722.2) and VMR-WB codecs. The decoder supports an inherent packet loss concealment algorithm and is also capable of decoding all the operating modes of G.722.2 codec. The codec is targeted for telephony/streaming applications on fixed, wireless, and mobile networks.

  • Based on ITU-T specification (06/2008).
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz or 16 KHz.
  • Support for 8 – 32 kbps bit-rates.
  • Support for the integrated noise suppression algorithm.
  • Support for configurable minimum noise suppression level ranging between 0 and 20dB.
  • Support for RTP payload format.
  • Support for integrated DTX mode of operation.
  • Support for configurable SID interval ranging between 1 and 100.
  • Support for low delay mode of operation.
  • Support for inter-operability with G.722.2 codec.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • The implementation supports both Little-Endian and Big-Endian (on C64x+ platform).
  • Optional support for xDM APIs for TI implementations.
  • Tested for bit-exactness with standard as well as a large database of non-standard test vectors.
  • Module is fully interruptible (Maximum interrupt latency on C64x+ is 6000 cycles).
  • Tested for any illegal memory access by the module (C64x+).
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Tested for Interoperability.
  • Range validation for all the API parameters.
  • Tested with scratch contamination at frame boundaries.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK.

TI C64x+ and TI C66x

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