Enhanced Variable Rate Codec (EVRC-A) was standardized as IS-127 in 1995. The EVRC codec operates on each 20ms frame of 16-bit speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates of 9.6 kbps (full-rate), 4.8 kbps (half-rate), or 1.2 kbps (one-eighth rate) respectively. It is based on Relaxed Code Excited Linear Prediction (RCELP) algorithm. The codec chooses the bitrate based on the analysis of the input speech and the current operating mode (either normal or one of the reduced rate modes). It includes an adaptive noise suppressor to handle background noise and is robust under frame erasures and channel errors. The codec was primarily developed for use in CDMA networks.

  • Based on IS-127/3GPP2 specification.
  • Optimized ASM/C implementation
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz.
  • Support for 9.6 kbps, 4.8 kbps, and 1.2 kbps bitrates.
  • The maximum and minimum bitrates can be configured during initialization.
  • The noise suppression module can be configured during initialization.
  • Support for RTP payload format as specified in RFC 3558.
  • Support for TTY/TDD signals as specified in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for post-filter operation, configurable at frame boundary.
  • Supports integrated DTX mode of operation.
  • Optional support for decoding of 3g2 streams.
  • Optional support for xDM APIs on TI platforms.
  • Little- and big-endian implementation on ARM.
  • Bit-exact with the standard test vectors (TI/ARM).
  • Module is fully interruptible.
  • ARM implementation tested for any illegal memory access.
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • AMD/Intel optimized floating-point implementation validated on Intel cores supporting SSE4 and above.

ARM9E, ARM11, Cortex-A8, Cortex-A9, TI C55x, TI C64x+, and AMD/Intel 64-bit cores supporting SSE4 and above.

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