EVRC-B

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EVRC-B

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Codec overview

Enhanced Variable Rate Codec B (EVRC-B) was standardized by 3GPP2 in 2006. The EVRC codec operates on each 20ms frame of 16-bit speech signals sampled at 8 KHz and generates compressed bit-streams with bit-rates of 8.3, 7.57, 6.64, 6.18, 5.82, 5.45, 5.08, and 4.0 kbps (source encoding rates) respectively. EVRC-B is based on the Code Excited Linear Prediction (CELP), Prototype Pitch Period (PPP), and Noise Excited Linear Prediction (NELP) coding algorithms. It makes greater use of the intermediate coding rates through increased awareness of the nature of the individual speech samples. This more sophisticated coding approach allows EVRC-B to offer a voice quality equivalent to EVRC-A (IS-127), but at significantly lower average coding bit rates. The codec was primarily developed to replace the existing EVRC-A codec used in CDMA networks.

Salient features

  • Based on 3GPP2 specification.
  • Optimized ASM/C implementation.
  • Re-entrant implementation.
  • C-callable APIs.
  • Operates on speech signals sampled at 8 KHz.
  • Support for selecting anchor operating mode or average rate mode during initialization time
  • Support for 8.3, 7.57, 6.64, 6.18, 5.82, 5.45, 5.08, and 4.0 kbps source encoding bit-rates.
  • The maximum and minimum bit-rates can be configured during initialization.
  • The noise suppression module can be configured during initialization.
  • Support for dim and burst, eighth rate hangover, and null traffic frame features specified in the standard.
  • Support for RTP payload format as specified in RFC 4788.
  • Support for DTMF and TTY/TDD signals as specified in the standard.
  • Supports integrated Packet Loss Concealment (PLC) algorithm.
  • Support for post-filter operation, configurable at frame boundary.
  • Supports integrated DTX mode of operation.
  • Support for setting the minimum and maximum DTX update interval during initialization
  • Little- and big-endian implementation on ARM and C6xx
  • Optional support for xDM APIs.

Testing features

  • Tested for bit-exactness with standard as well as a large database of non-standard test vectors.
  • Module is fully interruptible.
  • ARM and C6xx implementation tested for any illegal memory access.
  • Tested for compliance with register preservation requirements.
  • Tested for Input buffer corruption.
  • Tested for I/O buffer alignment requirements.
  • Tested for multi-instance implementation.
  • Tested for 100% code coverage.
  • Range validation for all the API parameters.
  • Tested with scratch contamination at frame boundaries.
  • Tested for packet loss conditions with 5% loss to 25% loss.
  • TI C55x implementation validated on Spectrum Digital C5510 DSK.
  • TI C64x implementation validated on Spectrum Digital C6416 DSK.
  • TI C64x+ implementation validated on Spectrum Digital C6455 DSK, DM6467, DM6446, and OMAP3530 platforms.
  • ARM implementation validated on OMAP3530 (Cortex-A8) and DM6446/DM6467 (ARM926EJ-S) platforms.
  • Intel optimized implementation validated on E2190 dual-core CPU.

Optimized implementation available on the following platform(s)

ARM9E, Cortex-A8, Cortex-A9, TI C55x, TI C64x, TI C64x+, and Intel cores supporting SSSE3 and above.

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